1. Field of the Invention
The present invention relates to a wiring structure and a method of manufacturing the same, and more particularly, it relates to a multilayer wiring structure and a method of manufacturing the same.
2. Description of the Background Art
A multilayer wiring structure is known in general.
A wiring structure of a semiconductor apparatus constituted by a first layer wiring (second wiring), an interlayer dielectric film (second interlayer dielectric film) formed on the first layer wiring, second layer wiring (third wiring) formed on the interlayer dielectric film is disclosed in general. The interlayer dielectric film is formed with a via hole having the same opening width from a lower end to an upper end, and the second layer wiring fills up the via hole.
In the conventional wiring structure of the semiconductor apparatus, however, the via hole has the same opening width from the lower end to the upper end and hence a portion where the second layer wiring has a small thickness is formed in the vicinity of an inner side surface of the via hole due to effects of shadowing (cumulatively reducing a growth rate of a portion shadowed in film formation) in forming the second layer wiring. In other words, coverage on the via hole by the second layer wiring is disadvantageously reduced. In this case, current density is increased on the portion where the coverage of the second layer wiring is reduced, and hence electromigration resistance is reduced. More specifically, a temperature of the portion where the second layer wiring has the small thickness is increased due to increase in the current density, and hence disconnection may be caused.